Modern digital electronic circuits are required to operate at increasing clock frequencies. At the same time there is a growing demand for compliance with stringent EMI/EMC standards. These requirements are contradictory in nature and therefore difficult to comply with. High-volume, low-cost integrated circuit implementations impose additional requirements of minimal silicon area utilization.
FIG. 1 shows a typical high-frequency clock generator circuit based on a Phase-Locked Loop (PLL) for generating a high frequency clock signal using a lower frequency input clock source. The input clock fin is fed to one input of Phase Difference Detector PDD. The output of PDD drives a Charge Pump CP for producing a control signal which, after smoothing by Low-pass filter LPF, is fed to the control input of a Voltage Controlled Oscillator VCO. The output of VCO is the high-frequency output clock fout. The VCO output is also fed back to a second input of PDD after being divided down in frequency by N-bit Divider DIV, thereby completing the control loop. This arrangement is likely to generate significant EMI owing to its narrow frequency emission spectrum.
Spread spectrum techniques offer a possible solution to meeting the requirements of EMI/EMC compliance. By using a spread spectrum clock as the source clock for that part of the logic which is switching at high speed the EMI emission of the device is significantly reduced and can be maintained within the limits set by regulatory bodies such as the FCC and CISPR. This technique distributes the energy of the clock signal, which is typically concentrated at its fundamental and harmonics, over a wider frequency band around the fundamental and harmonic frequencies thereby lowering the signal power level within a defined narrow frequency band. However existing methods of Spread Spectrum generation are limited in the effectiveness of the spectral distribution. In addition, these methods are expensive in terms of silicon area when implemented in integrated circuits.